Q3 2016
 
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SoC Solutions attends ARM Partner meeting

"Excitement is in the air regarding things to come with ARM's Cortex-M0 processor," says Jim Bruister after attending the ARM partner meeting in England last month.  

SoC Solutions will be a great asset for companies in need of additional IP and design resources when developing with ARM IP.

 

Partner Spotlight

SoC Solutions has partnered with leading silicon IP suppliers to provide both services and IP solutions.

For over 12 years, CAST has distributed our IP Cores. In many cases we have worked with CAST customers to not only provide IP, but to also provide design and integration services as an extension to CAST's product support.




In 2015, SoC Solutions joined the Constellations program in order to work with other IP and EDA companies to better support the design community.


SoC Solutions became one of the inaugural members of the ARM® Approved Design Partner program. SoC Solutions has worked with ARM and their products since our beginning in 2000.  You can find us in the ARM Connected Community.

SoC Solutions provides additional benefits to ARM's DesignStart Program
 
Announced earlier this year at DAC, ARM expanded its ARM® DesignStart™ program to include a list of approved design partners that can provide expert support during development and manufacturing.

SoC Solutions became one of the inaugural members of the ARM® Approved Design Partner program. ARM® DesignStart™ offers SoC designers free access to ARM Cortex®-M0 processor IP for design, simulation and prototyping with the option to buy a simplified and inexpensive, standardized fast track license.

SoC Solutions recognizes the need for additional IP needs. We have a series of our own proven IP cores such as DMA, QSPI, I2C, RTC and Security Cores often needed in your design projects.

SoC Solutions has a track record of success in design projects using ARM IP.

For more information about our services contact us.


 


AXI and AHB Multi-matrix Fabrics


We have AXI Multi-layer and AHB Multi-matix fabrics for your SoC interconnect or infrastructure.

The AXI Multi-layer Fabric provides the necessary infrastructure to connect as many as 8 shared AXI Slaves to as many as 4 AXI Bus Masters. Other features include AMBA AXI compatible, arbitration at each slave, 4 independent AXI channels, and address decoding and rounting in each channel.

The AHB Fabric may be used as either a partial or a complete AHB-Lite subsystem. Other features include AMBA 2.0 compatible, 4 AHB channels, supports 4 masters and up to 7 slaves, arbitration is done at each slave, and is easily expandable.
 
Please contact us for more information about our AXI and AHB Fabric IP and other AMBA® based products

 

 

Meet the new OctaSPI Controller.   The new-generation Serial NOR Flashes are expanding from the current Quad I/O to Octal (8) I/O for more data throughput while maintaing lower power.  SoC Solutions is meeting that interface need with our new OctaSPI core. The core will support the brand-new Data Transfer Rate (DTR) features, thus improving Execute in Place (XIP) performance and efficency.   Of course we still offer our QSPI Flash Memory Contoller (AHB and AXI) core to meet the “Small, Smart, Low Power” requirements of many IoT designs.  
See more>>>

 

       In Case You Missed It                           

Jim Bruister, President of SoC Solutions, appeared as a guest on IP Extreme's series Take Five with Warren Savage.  

According to IP Extreme, Jim "brings some southern style to the show. Jim shares his background in the tech industry (and in music!) and talks with Warren about walking the fine line between IP and services. It also gives us a glimpse into how the SoC Solutions team manages to be really great at both.

See the episode here>>>


 
SoC Solutions    49 Highway 23 NE    Suwanee, Georgia 30024     USA

Octal Serial Flash Controller Core

with Execute in Place (XIP)

AMBA® AXI4 and AHB Compatible

OctaSPI Blk dia

It's Here !

Meet the new Octal Serial Flash Controller.

The new-generation Serial NOR Flashes are expanding from the current Quad I/O to Octal (8) I/O for more data throughput while maintaing lower power. 

SoC Solutions is meeting that interface need with our new Octal SPI core. The core will support the brand-new Data Transfer Rate (DTR) features, thus improving Execute in Place (XIP) performance and efficency.


To meet the “Small, Smart, Low Power and Performance”, requirements many OEMs are considering using Octal SPI Flash memory chips from manufactures such as  Micronix. 

SoC Solutions provides a feature rich Octal SPI Flash Memory Controller to interface with these types of devices.

Request Information >

 

Features

  • Compatible with industry-standard serial FLASH devices
  • Execute-in-place (XIP)
  • AMBA AXI4 or AHB interface
  • DDR, DTR and SDR Support
  • DMA Interface
  • Octal, Quad, Dual and Single bit modes
  • 8 bit to 32 bit serial TX / RX
  • Separate SCLK input for Master Mode
  • 8 to 256 word TX / RX FIFO - configurable
  • Asynchronous Slave Interface
  • Interrupt control
  • LSB or MSB mode
  • Up to 4 slaves under Master control

Overview

The Octal Serial Peripheral Interface core is designed to interface an AMBA AXI4 or AHB processor bus to a number of the new Octal Serial Flash Memory devices from memory manufacturers such as Macronix.  The controller is specifically designed for IoT, M2M and low power applications but is useful in applications such as Automotive, Connected Home, Medical devices and others.

The Octal Serial Flash controller can be configured under software control to be a master or slave device.  Reading and writing the core is done on the AMBA® AXI4 or AHB bus interface.  The core operates in various data modes from 8 bits to 32 bits (8 modes are supported in multiples of 8 data bits).  The data is then serialized and then transmitted, either LSB or MSB first, using the standard 4-wire SPI bus interface or the extended Dual, Quad, and Octal Bus modes. 

The Octal Serial Flash module is compatible with various industry-standard DMA controllers. DMA operation in the core can be enabled to assist a DMA controller in the loading (writing) of the transmit FIFO, and the unloading (reading) of the receive FIFO. 

The Execute in Place (XIP) Mode allows an AMBA Master to directly read the contents of the Flash Memory simply by reading from the address space of the Octal Serial Flash controller.

 

SPI Slave Monitor IP Core

(IPC-SpiAhbLiteBridge-AHB)

Debug Monitor for accessing internal memory and registers

AMBA® AHB Compatible

 

SpiSlaveMonitor 

 

For more information

Request Information >

 

Features

  • SPI Slave - AHB Master
  • Useful as a monitor and debugger
  • Allows access internal SOC memory and registers
  • Useful for production configuration
  • Useful for manufacturing testing

Overview

The SPI Slave Monitor IP core is commonly used as an interface to allow external devices to access the internal AHB bus.

A SPI Slave to AHB Lite Interface block (socSpiAhbLiteBridge) is included to provide read/write access by an external SPI device to the various memories and registers that are present in the chip's internal AHB Lite subsystem.  The Bridge converts SPI transactions into AHB Read or Write instructions, allowing the external SPI device to have full access to all memory mapped devices present in the AHB Lite subsystem.

The SPI Bridge block consists of a low-level SPI interface and a SPI protocol layer. 

The low-level SPI interface is clocked by the SPI bus clock (provided by the external SPI device), and is responsible for several things including:

  • Serializing the MISO data going to the external device.
  • Creating a synchronizing pulse to the system so that the system can drive/sample data
  • De-serializing the MOSI data coming from the external SPI device.

The SPI protocol layer is clocked by the system fast clock.  The SPI protocol layer is responsible for several things including:

  • Interpreting commands from the low-level SPI interface as read, write, or write burst.
  • Presenting (parallel) address and write data from the low-level SPI interface to the system.
  • Generating a one-clock-wide write strobe to the system timed with the presence of write data.
  • Presenting (parallel) read data from the system to the low-level SPI interface.

QSPI with Execute in Place (XIP)

IP Core

Quad SPI Master/Slave Controller

AMBA® AXI4 Compatible

QSPI AXI blk dia 

The trend in electronic devices today is “Small, Smart, Low Power" devices that provide information to a network to be collected in a cloud.   Internet of Things, Machine to Machine, Infotainment, Cameras, Smart TVs, Smart Meters or Smart Grids are just a few of the applications requiring non-volatile, FLASH memory. 

To meet the “Small, Smart, Low Power”, requirements many OEMs are using QSPI Flash memory chips from manufactures such as Micron, Micronix, Winbond and Spansion. 

SoC Solutions provides a feature rich QSPI Flash Memory Controller to interface with these types of devices.

Request Information >

 

Features

  • Compatible with many industry-standard serial FLASH devices
  • Execute-in-place (XIP)
  • AMBA AXI4 interface
  • DMA Interface
  • Master or Slave mode
  • Single, Dual and Quad-bit modes
  • 4 bit to 32 bit serial TX / RX
  • Full duplex operation
  • Half duplex operation support
  • Separate SCLK input for Master Mode
  • 8 to 256 word TX / RX FIFO - configurable
  • Asynchronous Slave Interface
  • Interrupt control
  • LSB or MSB mode
  • Up to 4 slaves under Master control
  • Motorola Serial Peripheral Interface (SPI) format support
  • TI Synchronous Serial Frame format support
  • National Microwire Frame format support

Overview

The Quad Serial Peripheral Interface module either controls a serial data link as a master, or reacts to a serial data link as a slave.    

The IPC-QSPI-AXI bus controller can be configured under software control to be a master or slave device.  Reading and writing the core is done on the AMBA® AXI bus interface.  The core operates in various data modes from 4 bits to 32 bits (8 modes are supported in multiples of 4 data bits).  The data is then serialized and then transmitted, either LSB or MSB first, using the standard 4-wire SPI bus interface or the extended Dual or Quad Bus modes. 

The IPC-QSPI-AXI module is compatible with various industry-standard DMA controllers. DMA operation in the IPC-QSPI-AXI can be enabled to assist a DMA controller in the loading (writing) of the transmit FIFO, and the unloading (reading) of the receive FIFO. 

The Execute in Place (XIP) Mode allows an AXI Master to directly read the contents of any of several industry-standard FLASH devices (such as Winbond, Macronix, Spansion and Micron devices) simply by reading from the address space of the QSPI Controller. 

The IPC-QSPI-AXI can be used with up to four SPI slave devices.