QSPI IP Core

Quad SPI Master/Slave Controller

AMBA® AHB Compatible

 

The trend in electronic devices today is “Small, Smart, Low Power" devices that provide information to a network to be collected in a cloud.   Internet of Things, Machine to Machine, Infotainment, Cameras, Smart TVs, Smart Meters or Smart Grids are just a few of the applications requiring non-volatile, FLASH memory. 

To meet the “Small, Smart, Low Power”, requirements many OEMs are using QSPI Flash memory chips from manufactures such as Micron, Micronix, Winbond and Spansion. 

SoC Solutions provides a feature rich QSPI Flash Memory Controller to interface with these types of devices.

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QSPI blk dia

 

 

Features

  • Execute-in-place (XIP) functionality for industry-standard FLASH devices
  • 4 bit to 32 bit serial transmit & receive
  • Full duplex operation
  • Half duplex operation support
  • Software programmable Master or Slave mode
  • Software programmable SCLK rate for Master mode
  • Quad-bit mode operation
  • Dual-bit mode operation
  • separate SCLK input for Master Mode
  • 64 word Transmit FIFO
  • 64 word Receive FIFO
  • Asynchronous Slave Interface
  • AMBA AHB interface
  • Interrupt control
  • LSB or MSB mode
  • Up to 4 slaves under Master control
  • Tristate Slave MISO signaling for multiple slaves
  • DMA Interface
  • Compatible with many industry-standard FLASH devices
  • Additional GPOs/GPIs to aid with unusual signaling requirements

Overview

The Quad Serial Peripheral Interface module either controls a serial data link as a master, or reacts to a serial data link as a slave.    

The IPC-QSPI-AHB bus controller can be configured under software control to be a master or slave device.  Reading and writing the core is done on the AMBA® AHB bus interface.  The core operates in various data modes from 4 bits to 32 bits (8 modes are supported in multiples of 4 data bits).  The data is then serialized and then transmitted, either LSB or MSB first, using the standard 4-wire SPI bus interface or the extended Quad mode bus. 

Data is transmitted synchronously with MOSI (Master Out, Slave In) relative to the SCLK generated by the master device.  The master also receives data on the MISO (Master In, Slave Out) signal in a full duplex fashion.  

In Quad mode operation, four bits are output and input simultaneously, and the msb is always sdataOut[3]/sdataIn[3].  In Dual mode operation, two bits are output and input simultaneously, and the msb is always sdataOut[1]/sdataIn[1].  In single bit operation only sdataOut[0] and sdataIn[0] are used.