SPI Slave Monitor IP Core


Debug Monitor for accessing internal memory and registers

AMBA® AHB Compatible




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  • SPI Slave - AHB Master
  • Useful as a monitor and debugger
  • Allows access internal SOC memory and registers
  • Useful for production configuration
  • Useful for manufacturing testing


The SPI Slave Monitor IP core is commonly used as an interface to allow external devices to access the internal AHB bus.

A SPI Slave to AHB Lite Interface block (socSpiAhbLiteBridge) is included to provide read/write access by an external SPI device to the various memories and registers that are present in the chip's internal AHB Lite subsystem.  The Bridge converts SPI transactions into AHB Read or Write instructions, allowing the external SPI device to have full access to all memory mapped devices present in the AHB Lite subsystem.

The SPI Bridge block consists of a low-level SPI interface and a SPI protocol layer. 

The low-level SPI interface is clocked by the SPI bus clock (provided by the external SPI device), and is responsible for several things including:

  • Serializing the MISO data going to the external device.
  • Creating a synchronizing pulse to the system so that the system can drive/sample data
  • De-serializing the MOSI data coming from the external SPI device.

The SPI protocol layer is clocked by the system fast clock.  The SPI protocol layer is responsible for several things including:

  • Interpreting commands from the low-level SPI interface as read, write, or write burst.
  • Presenting (parallel) address and write data from the low-level SPI interface to the system.
  • Generating a one-clock-wide write strobe to the system timed with the presence of write data.
  • Presenting (parallel) read data from the system to the low-level SPI interface.