Proven IP Subsystems

Since our beginning we have believed in the idea that "It's the System that is important".  A good system level design is crucial to designing a successful product.  This is certainly true for SOCs.  Our subsystems have been designed with the total system in mind.  That's why our subsystems are delivered with the infrastructure (bus systems), memory systems and peripherals all in a verification environment that emulates the software and hardware together...at a system level

Our IP Subsystem environment is easily expanded to include your peripherals or special interfaces.  Our Verilog/SystemVerilog based verification environments make it easy to use with any of the standard simulation tools from Cadence, Mentor Graphics or Synopsys.  

All of our peripherals, DMAs, buses and memory controllers are delivered with comprehensive stand-alone tests using AMBA® standard transaction or Bus Functional Models (BFM).  See Proven IP Cores.

 Ask about subsystem tailored to your needs.  See Custom Platforms.  Request Information >

 

 

 

Low Power

Features:

  • Supports Cortex-M0 (or equivalent) processor.  
  • Power Management Unit
  • AMBA® 3.0 (AHBLite)
  • AHB/APB Bus infrastructure
  • Internal SRAM controller
  • Standard APB Peripheral package
    • I2C, SPI, UART, GPIO, Timers, Watchdog

Low Power / Performance

Features:

  • Supports Cortex-M3/M4 (or equivalent) processor
  • Power Management Unit
  • AMBA® 2.0 (AHB)
  • AHB Multi-matrix bus infrastructure
  • External Nor Flash controller
  • DMA (single or multi-channel)
  • Internal SRAM controller
  • Interrupt Controller (optional)
  • QSPI with Execute in Place (XIP) for standard Flash parts such as Winbond and Spansion
  • AHB/APB bridge
  • Standard APB Peripheral package
    • I2C, SPI, UART, GPIO, Timers, Watchdog

Performance

Features:

  • Supports Cortex-A5 (or equivalent) processor
  • AMBA® 4.0 (AXI)
  • AXI Multi-layer bus infrastructure
  • External Nor Flash controller
  • DMA (single or multi-channel)
  • DDR2/3 support (3rd party IP)
  • Internal SRAM controller(s)
  • Interrupt Controller (optional)
  • QSPI with Execute in Place (XIP) for standard Flash parts such as Winbond and Spansion
  • AXI/APB bridge
  • Standard APB Peripheral package
    • I2C, SPI, UART, GPIO, Timers, Watchdog
  • AXI-AHBLite bridge (optional)